1. Field of the Invention
The present invention relates to a compiling method, particularly to a power-aware compiling method.
2. Description of the Related Art
Recently, portable products, such as PDA, mobile phones and MP3 players, become more and more popular. In addition to the compactness of appearance, standby time is also a factor influencing consumers' decisions. Thus, battery runtime becomes a critical factor to evaluate a portable product. Increasing battery runtime not only can reduce the size, weight and cost of a portable product but also can raise the price of the portable product. Therefore, how to increase battery runtime has become a hot topic.
Currently, there are essentially three technologies to reduce the power consumption of portable products. The first one is to solve the power-consumption problem from a hardware approach, wherein special hardwares are used to reduce power consumption, such as the DVS (Dynamic Voltage Scaling) technology proposed by Intel Corp., etc., which modifies the voltage and frequency of a processor to efficiently utilize the processor and avoid unnecessary power consumption; however, the performance of the processor will be obviously influenced. The second one is to solve the power-consumption problem from an operating-system approach, wherein the operating system is modified to reduce power consumption, and the sequence of execution threads is rescheduled to prevent the appearance of the peak busy period; however, recalculation and rescheduling caused by adding a new execution thread will degrade the performance of the processor. The third one is to solve the power-consumption problem from a compiler approach, wherein during compilation, power-related information is added into the program codes to instruct the processor to modify the voltage and frequency; thus, the processor can be efficiently used, and unnecessary power consumption can be avoid; however, such a technology requires a hardware compatibility.
From those discussed above, three phenomena can be observed. The first one is: it is hard to achieve a high power efficiency and a high performance at the same time; if the power efficiency is high, the performance will be low; if the performance is high, the power efficiency will be low. The second one is: some solutions can only apply to special platforms. The third one is: some solutions have to dynamically calculate appropriate voltage and frequency, which delays the processor.
Accordingly, the present invention proposes a power-aware compiling method to overcome the abovementioned problems.